1. ä¿ëºÐ¾ß
¡à FPGA Engineer
- VHDL, Verilog±â¹Ý RTL ¼³°è
- Simulation Model ¹× Testbench ¼³°è
- RTL Simulation ¹× Verification
- FPGA Built in logic analyzer »ç¿ë °æÇè (Chip Scope/Signal Tap)
- DDR Memory, LVDS, MIPI Interface Block »ç¿ë °æÇè
- Xilinx Zynq ±â¹Ý FPGA °³¹ß °æÇè ¿ì´ë(AXI »ç¿ë °æÇè)
2. Áö¿øÀÚ°Ý
- ÇзÂ: Çлç ÀÌ»ó
- °æ·Â: 5³â ÀÌ»ó
3. ±Ù¹«Áö
- °æ±â ÆDZ³