¾È³çÇϼ¼¿ä?
¶óÀμ­Ä¡ÀÇ ÇìµåÇåÅÍ ¹ÚÇü±Ô ´ëÇ¥ÀÔ´Ï´Ù.
ÀúÈñ´Â ¹ÝµµÃ¼,µð½ºÇ÷¹ÀÌÆÀ/ÀüÀÚ,ITÆÀ/±â°è,È­ÇÐÆÀ/Á¦¾à,¹ÙÀÌ¿ÀÆÀÀ» ÁÖÃàÀ¸·Î 
ÃÖ°í ÀÓ¿ø±ÞÀ» ºñ·ÔÇÏ¿© °¢ºÐ¾ß ½Ç¹« Àü¹®°¡µéÀ»
Ãßõµå¸®´Â ÇìµåÇåÆÃ¾÷°è¸¦ ¸®µùÇÏ´Â Àü¹®È¸»çÀÔ´Ï´Ù.
ÁÁÀº Æ÷Áö¼ÇÀ» Ãßõµå¸³´Ï´Ù.


[Æ÷Áö¼Ç]
PI¿£Áö´Ï¾î

[´ã´ç¾÷¹«]
°³¹ß SoC¿¡ ÀûÇÕÇÑ Logic level ±¸Çö ¹× °ËÁõ
°í¼º´ÉCPU, °í¼ÓInterface IPµîÀÇ Complex clock±¸Á¶¿¡ µû¸¥ Timing Methodology ±¸Çö
UPF ±¸Çö ¹× Low Power Specific SoC °³¹ß
Design Flow, Signoff Methodology °³¹ß ¹× ±¸Çö

ASIC Frontend Implementation    
 - Logic Synthesis, STA, SDC Clean, Formal Verification    
 - Low Power Implementation, UPF design flow    
 - SCAN, ATPG, Memory BIST    
 - High Speed IP (DDR5/PCIe/NANDPHY) Implementation

[¿ì´ë»çÇ×]
 - High Speed IP (DDR5/PCIe/NANDPHY) Implementation  ¹× Test Scheme ±¸Çö °æÇèÀÚ ¿ì´ë    
 - FinFET °æÇèÀÚ ¿ì´ë


°æ·Â°ú ¸ÅĪµÇ½Ã´Â ºÐÀº
******@*******.***·Î À̷¼­¸¦ º¸³»Áֽðųª,
***-****-****·Î ¹®Àǹٶø´Ï´Ù.
°¨»çÇÕ´Ï´Ù.