[담당업무]

ㆍDFT Implementation

ㆍSCAN insertion / ATPG / Scan Simulation (Test Compiler / TetraMax)

ㆍBIST/BIRA Insertion & Simulation: Tessent MBIST / JTAG / IJTAG

ㆍSDC Creation & Clean

ㆍSpyglass LINT/SDC/DFT Check

ㆍLogic Synthesis: DC/DCT/DCG

ㆍEquivalence Check: Formality/Conformal

ㆍLDRC: Logic Design Rule Check (Spyglass_LDRC)

ㆍSTA (Static Timing Analysis)

ㆍTiming Closure: cross-talk/noise/mttv/setup/hold fix

(Prime_Time, Physical-aware ECO)

ㆍLow Power Design: UPF Creation & Low power Rule Check(VC_LP)

ㆍMulti-voltage, Multi power domain, Power-gating, Clock-gating.

ㆍPower Analysis: Vectored / Vectorless (PTPX)

ㆍImplementation 자동화 Platform 개발

ㆍSimulator & Debugger: VCS / NC-verilog / Verdi

-Key Performance Measures

ㆍUnderstanding SoC/ASIC design flow.

ㆍPerform Hierarchical Implementation(SYN/DFT/STA/UPF)

in Samsung 14nm or less process.

[자격요건]

ㆍ4년제 대졸 이상

ㆍScripting (shell, tcl, perl, phython, etc.)

ㆍVersion Control system (Git, CVS, ClearCase, Perforce, etc.)

ㆍBus protocol (AMBA, NoC etc)

ㆍBusiness English (Business letter/email reading & writing etc.)

[우대사항]

ㆍDFT 전문성 보유

ㆍTop level DFT Architecture 설계 경험자

ㆍHPDF DFT 경험자 (Top/Block level)

ㆍATE Vector setup 및 Yield 개선 업무 경험자

ㆍIJTAG(IEEE1687) 경험자 ( Tessent tool 이용 )

ㆍHierarchical implementation Flow 경험자

ㆍSEC 14nm 이하 공정 경험자

ㆍCPU (ARM Cortex Series, RISC-V 등) 1.0 GHz 이상 Hardening 경험

ㆍDVFS implementation 경험.

ㆍHSI IP Hardening 경험자

(LPDDR4 PHY / PCIe PHY / Ethernet PHY / SerDes PHY)

ㆍ설계 자동화 platform 개발 경험자

ㆍHigh-frequency Bus 구현 경험자