KOSDAQ ¾çÀÚº¸¾È¾÷ü
SoC Ĩ°³¹ß
¸ðÁýºÎ¹® ¹× ÀÚ°Ý¿ä°Ç
| ¸ðÁýºÎ¹® | ´ã´ç¾÷¹« | ÀÚ°Ý¿ä°Ç | Àοø |
|---|---|---|---|
SoC Ĩ°³¹ß |
[´ã´ç¾÷¹«] - SoC Top Integration °³¹ß ¹× °ËÁõ - Verilog, System Verilog HDL coding ¹× Simulation - Cadence, Synopsys EDA tool (EQC, Spyglass, Design Compiler µî) - SoC RTL ÇÕ¼º ±â¼ú½ºÅØ verilog systemverilog UVM C/C++ Embedded System Verification |
[ÀÚ°Ý¿ä°Ç] - CPU(Cortex-M°è¿, RISC-V°è¿)±â¹Ý SoC°³¹ß - F/W ¸¦ ÀÌ¿ëÇÑ SoC °ËÁõ °æÇè ¿ì´ë»çÇ× - UPF, low power design, PrimeTime-PX °æÇè - Peripheral IP °³¹ß ¹× °ËÁõ °æÇè - Design Compiler scripting °³¹ß °æÇè - FPGA °ËÁõ °æÇè |
0 ¸í |
±Ù¹«Á¶°Ç
ÀüÇü´Ü°è ¹× Á¦Ãâ¼·ù
Á¢¼ö¹æ¹ý
±âŸ À¯ÀÇ»çÇ×
00